Essentially all devices needed to make the equivalent of a modern digital or analog circuit out of nanotubes and/or nanowires have been demonstrated in prototype experiments, and elementary logic circuits have been demonstrated. Various researchers have claimed that nanowire/nanotube devices are superior to CMOS in various metrics, such as transconductance per width or mobility. When properly phrased, these claims are true. The underlying, unspoken motivation remains, however, that the devices are or can be smaller than spatial resolution limits posed by lithography, which would provide a route to extend Moore's law into the domain of nanotechnology.
The nanotube and nanowire devices developed to date have been contacted by lithographically fabricated electrodes. This is not a scalable technique for massively parallel processing, integrated nanosystems, due to the geometrical limits of lithography. The potential high-density circuitry possible with nanowires and nanotubes will not be realized if each nanowire and nanotube is contacted lithographically.
Fault-tolerant architectural schemes have recently been proposed to tackle this interconnect problem. For example, using N lithographically fabricated wires, it is possible to address individually 2N nanowires using a binary-tree multiplexing scheme. Since the spacing between the nanowires is beyond the limits of lithography, the electrical connections between the nanowires and lithographically fabricated wires are random, but could in principle be measured after the manufacturing process. With this technique, each chip manufactured would have its own unique firmware, specific to the nano-level physical hardware defects.
However, a more manufacturable interconnect is needed that allows efficient implementation and full scalability of integrated nanosystems.